| General |
|
| PCI-X/PCI bus |
32/64-bit, up to 133 MHz |
| Interfaces |
USB port, 12 Mb/s.
Ethernet port 10/100 Mb/s |
| Power supply requirements |
+3.3VDC +/-5% from CompactPCI connector. |
| Power consumption |
5V Max 1.0A
3.3V Max 4.0A |
| Dimensions |
3U (100 mm by 160 mm) |
| Compliant to |
PCI rev 2.3
PCI-X 1.0a.
PICMG 2.0 R3.0,
PICMG 2.1 Hot Swap R2.0,
PICMG Specification ECR R0.6a to PICMG 2.0 R3.0 |
| Measurements |
Temperature probe: 0-120 °C / 32-248 °F
Voltage: 3.3V, 5V, 12V |
| Operating temperature |
0-50 °C/ 32-122 °F |
| |
|
| Analyzer |
|
| Trace Memory |
2M Samples x 256 bits (64 MBytes total) |
| Input channels |
96 bus signals, plus 16 ext. inputs |
| PCI-X/PCI clock requirements |
Max. 133 MHz, min. 1 kHz |
| Signal levels |
3.3V or 5V |
| Monitored signals |
AD[31::0], AD[63::32], C/BE[3::0]#, C/BE[7::4]#, FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#, PAR, PAR64, PERR#, SERR#, RST#, INTA:D#, LOCK#, ACK64#, REQ64#, REQ#, GNT#, IDSEL, PME#, INTS, INTP, ENUM#. (Plus GNT3:0#, REQ3:0#, IDSEL via pin headers), REQ1#, GNT1# (System Slot only) |
| Trigger |
8 word recognizers covering all 93 PCI signals and 16 Ext. inputs. True Range & NOT operator on Address/Data. Edge Triggering. |
| Range |
8 A64 address ranges, 8 D64 data ranges. Inside/Outside. |
| Sequencer |
16 levels with If, Else, Elsif, Goto, Count, Delay, Trigger, Store, Halt. |
| Trigger position |
0-100%, 1% resolution |
| Occurrence / delay counters |
3 x 32-bits |
| Event counters |
8 x 30-bits for Statistics |
| Real-Time Statistics Counters |
47 x 30-bits counters |
| Decode Speed Counter |
1 dedicated counter |
| Time Tag |
Range: 30ns-4688min@33MHz, 15ns-2344min30sec@66MHz, 10ns-1562 min@100MHz, 7.5ns-1172min@133MHz
Resolution: 30ns@33MHz, 15ns@66MHz, 10ns@100MHz, 7.5ns@133MHz |
| Latency Tag |
Counts latency (wait states) from FRAME# to TRDY# asserted. Max count: 64 clocks. |
| Trigger Output |
LVTTL level trigger output with programmable polarity, level or pulse. May pulse on each stored sample. Available on pin header in front panel. |
| External Inputs |
8 TTL level inputs on pin header. 8 TTL level inputs on front panel |
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|
| Exerciser |
|
| Master |
Zero-wait-states, 1 GB/s @133 MHz peak burst rate, 64-bits Address (PCI-X only), 2 DMA Controllers. |
| Target |
8 MB SDRAM memory, 1 GB/s peak burst rate @133 MHz. 32/64-bit address. 256 byte I/O space memory. |
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|
| Protocol Checker |
| PCI-X Violations |
71 Protocol Violations |
| PCI Violations |
45 Protocol Violations |
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| System Controller |
| Clock Generator |
25, 33, 50, 66, 100 and 133 MHz |
| Arbiter |
REQ[0:7], GNT[0:7] monitored |