Phoenix 3CPF1 - PowerPC 744X and User Programmable Virtex-II Pro FPGA 3U DSP Board

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3CPF1-ENC-0001 - 3U enclosure with 7 slot backplane

Overview
Block diagram
Specification
Ordering info
Datasheet

PowerPC Nodes
Processor	1 GHz PowerPC 7447A
FLASH	64Mbytes
Bridge	Marvell MV64360
SDRAM	256 or 512Mbytes
Ethernet	2x 10/100Mbps (or 1Gbps)
Serial I/O	1x RS232, 1x RS422 (with RTS/CTS)

FPGA Nodes
FPGA	XC2VP50 or XC2VP70
Maximum Rocket IO Speed	3.125Gbps (-6 speed grade)
SDRAM	128Mbytes with ECC (2x banks 64Mbytes)
QDR SRAM	4 banks 4Mbytes per bank 18-bit data paths

Inter-Node Communications
PowerPC to/from FPGA	64-bit/125MHz PCI-X

Off-board Communications
Parallel Bus	32-bit, 33MHz PCI
High-Speed Serial	8x 2.0/3.125Gbps (from FPGA node)
Ethernet	2x 10/100/1000Mbps (from PowerPC node)
Serial I/O	1x RS232, 1x RS422 (with RTS/CTS)

Debugging
JTAG	COP (PowerPC) chain ChipScope (FPGA)

Software Support
Operating Systems	VxWorks/PowerPC Linux/PowerPC - Beta available, please call VMETRO
Libraries	Signal & Image Processing (PowerPC)
Other	Built-In Test (BIT)

3CPF1-2C-2-76-2-1-A	1GHz PowerPC 7447A with - 256 Mbytes DDR SDRAM - 64 Mbytes FLASH XC2VP70 FPGA (-6 speed grade) with - four banks 2Mx18bit QDR SRAM - two banks of 64Mbytes SDRAM - 156.25MHz BREF clock (3.125Gbps high-speed serial comms) Commercial environmental build
3CPF1-2C-2-76-2-2-A	1GHz PowerPC 7447A with - 256 Mbytes DDR SDRAM - 64 Mbytes FLASH XC2VP70 FPGA (-6 speed grade) with - four banks 2Mx18bit QDR SRAM - two banks of 64Mbytes SDRAM - 156.25MHz BREF clock (3.125Gbps high-speed serial comms) Level 2 Air-cooled environmental build*
3CPF1-2C-2-76-2-4-A (minimum order quantity of 3)	1GHz PowerPC 7447A with - 256 Mbytes DDR SDRAM - 64 Mbytes FLASH XC2VP70 FPGA (-6 speed grade) with - four banks 2Mx18bit QDR SRAM - two banks of 64Mbytes SDRAM - 156.25MHz BREF clock (3.125Gbps high-speed serial comms) Conduction-cooled environmental build

Call for availability of boards fitted with other MC744x processors. Related Products

3CPF1 Adapters/Transition modules
3CPF1-TRANS-A	3CPF1 Transition module for standard 3U Compact PCI backplanes - requires 3CPF1 adapter (below)
3CPF1-ADAPT-SYS	Conversion to a standard 32-bit, 3U CompactPCI backplane System Slot - for development/evaluation only
3CPF1-ADAPT-PER	Conversion to a standard 32-bit, 3U CompactPCI backplane Peripheral Slot - for development/evaluation only
3CPF1-SER-1	3U RS232 serial I/O card to break out backplane RS232 signals from processor cards in a 3CPF1-BP1
VPF1-DEBUG	FPGA & PowerPC Boundary Scan adaptor module (includes ChipScope FPGA ILA headers)

Software
CD-PX	Power/FPGA VxWorks BSP and Utilities for Phoenix 3CPF1. Project/Site License including one year maintenance and support.
CD-PXL	Linux Distribution for Phoenix 3CPF1. Project/Site License including one year maintenance and support.
CD-PX-SUPPORT	Annual Maintenance
CD-VSIPLUS	VSIPLus Libraries bundle

Enclosures/Backplanes
3CPF1-ENC-0001	6U Enclosure for Phoenix 3CPF1 Processors (Includes 650W PSU and 3CPF1-BP1)
3CPF1-BP1	Phoenix 3CPF1 Backplane only

1GHz PowerPC 7447A CPU node
Xilinx Virtex-II Pro FPGA node
8x 2.0-3.125Gbit/sec off-board serial communications channels
High density parallel data I/O ports
Gigabit Ethernet, RS232, RS422
PCI bus to backplane
VxWorks, Linux operating systems
Embedded FPGA processing cores
Built-In Test (BIT)
Optimized VSIPL DSP libraries
Air-cooled and rugged conduction-cooled build variants

The Phoenix 3CPF1 is a modular signal and data processing engine harnessing the combined power of PowerPC CPUs, large Xilinx™ FPGAs and high-bandwidth multichannel serial communication fabric. This creates a balanced and scalable compute platform for radar, sonar, electronic warfare and real-time imaging applications.

A complete rugged and systems based roadmap, means that the Phoenix 3CPF1 can be used as a common building block to a range of systems and results in accelerated development cycles and fast time-to-market.

PowerPC
The PowerPC processor node is a fully self-contained processor complete with memory, bus and network interfaces. The 1GHz PowerPC 7447A comes with 256 or 512Mbytes of DDR SDRAM (with ECC) and is globally accessible. The memory is coupled to the PowerPC CPU via a Marvell MV64360 bridge which also provides two Gigabit Ethernet channels, RS422s and RS232 ports as well as a PCI interfaces. The SDRAM is implemented with 72-bit datapaths and clocked at 125MHz for an effective data rate of up to 2Gbytes/sec. 64Mbytes FLASH memory is available.

Ethernet + RS422 & RS232 Interfaces
Two off-board Gigabit Ethernet interfaces are provided from the PowerPC processor node. The off-board interfaces are routed to the backplane, though a build option allows routing to RJ45 front panel connectors for non conduction-cooled variants. One RS422 interface with RTS/CTS handshaking and one RS232 port are also provided. These ports are also made available to a backplane connector. Both ports are fully available for user applications and can be used for a serial console as required by VxWorks for boot configuration.

Virtex-II Pro FPGAs
The Phoenix 3CPF1's FPGA node is based around the Xilinx XC2VP70 Virtex-II Pro device. The node is provided with eight 2.0/3.125Gbps SERDES transceiver pairs, a 64-bit/125MHz parallel bus to it's adjacent PowerPC bridge, four banks of 2M x 18-bit QDR SRAMs and two banks of 64/128Mbytes DDR SDRAM (both memory types are directly linked to the FPGA for maximum flexibility) and a JTAG port.

The FPGA's configuration file is supplied by the attached PowerPC processor and is stored in the PowerPC CPU's FLASH. VMETRO development tools facilitate programming the FPGA in both development and run-time environments. JTAG can also be used for FPGA configuration during development. An onboard battery build option is available so that encrypted keys can be stored for secure FPGA configurations.

Gigabit Serial Communication Channels
The Virtex-II Pro FPGA features 2.0/3.125Gbps RocketIO transceivers channels. Eight channels from the FPGA are available for off-board communications. Groups of RocketIOs from a single device can be 'bonded' together to synthesize higher bandwidth data links.

Software
The BSP library provides integration support for using the Phoenix 3CPF1 from within a host application. It is a C++ library supporting general hardware access and the implementation of high-speed DMA routines. Full source code for the libraries is supplied. Example programs using these library routines are included to perform such tasks as setting up various DMAs to and from the board and interrupt handling.

The host services provided by the libraries usually requires the support of an operating system dependent device driver. Drivers for VxWorks and Linux operating systems will be supported.

Host utilities are provided to give the user a graphical user interface with a complete view of the board hardware (registers, memory, etc.). Other utilities allow for system evaluation and functional testing, as well as configuring the FPGA from the host and loading the FLASH.

Last updated: Aug 08 2008, 04:05PM

PowerPC 744X & Virtex-II Pro FPGA 3U Card

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Phoenix 3CPF1 PowerPC 744X and User Programmable Virtex-II Pro FPGA 3U DSP Board