MM-7115 PMC FPGA Compute Node with User Programmable Virtex-4 LX200 and LX160 FPGAs

In terms of logic resources, the MM-7115 is the most powerful FPGA processing engine ever to be offered on the PMC form factor. By combining Xilinx’s largest Virtex-4 FPGAs, the LX200 and LX160, the MM-7115 addresses the most demanding signal processing requirements in a modular, flexible PMC form factor.

The MM-7115 can be utilized on PowerPC and x86 Single Board Computers, Altivec DSP boards, A/D converters, graphic engines or any carrier that has a PCI Mezzanine Card (PMC) site. The MM-7115 module’s primary bus that interfaces to the host system is located in the LX200 FPGA. This PCI/PCI-X bus provides a data transfer, communication and control plane to the rest of the system. It supports 32-bit and 64-bit PCI transfers at 33MHz/66MHz, or 64-bit PCI-X transfers at 66MHz/133MHz, and is compliant with the with IEEE P1386/P1386.1 CMC/PMC draft standard and ANSI/VITA 20-2001 (R2005).

CoSine IP
The optional CoSine bitstream consists of a PCI/PCI-X bus interface, specialized PCI DMA engine, UPL DMA engine, multi-ported DDR2 memory controller with ECC, and high bandwidth inter-FPGA interface. Unlike other solutions which only provide IP in the form of individual cores that require customers to perform complicated integration, the CoSine IP is optionally offered as a totally preconfigured solution with fixed IP placement and timing constraints to minimize customer development efforts.

The CoSine Development Kit includes a VHDL wrapper with well defined interfaces, extensive VHDL test benches and host system diagnostics in C for complete verification of custom user programmable logic implementations. A demo program with a fully functional 1K FFT implementation is also provided with VHDL source code to the glue logic and wrapper interface that can serve as a working baseline and reference design. Extensive documentation such as the CoSine UPL Developer’s Guide is also included in the CoSine Development Kit.

Memory Array & Controller
A 72-bit wide DDR2 memory array is local to the Virtex-4 LX200 FPGA and can be configured as 256MB, 512MB, or 1GB of high speed memory. The DDR2 controller includes ECC that detects double bit errors and corrects single bit errors. This high speed multi-ported DDR memory controller can support concurrent accesses between the external PCI/PCI-X bus and internal User Programmable Logic (UPL).

DMA Engines
The MM-7115 has two DMA engines, a PCI/PCI-X Mailbox DMA engine and a UPL DMA engine. The PCI/PCI-X Mailbox DMA engine writes a semaphore into host memory upon the completion of a DMA transfer so that the host CPU does not need to poll for DMA status completion. It also provides scatter/gather and link list capabilities for DMA chaining. The UPL DMA engine is local to the User Programmable Logic block and can be directly programmed by the host carrier’s CPU.

Inter-FPGA Interface
The interconnect between the two FPGAs is based on a full-duplex LVDS implementation that provides over 3GB/s of full duplex, low latency bandwidth.

Logic Resources
It is often difficult to predict FPGA logic resource utilization requirements in advance of RTL implementation. This concern is greatly alleviated by the LX200 which provides 200,448 logic cells, or 89,088 FPGA slices, that roughly translates to over 20 million conventional ASIC gates and the most logic resources of any Xilinx Virtex-4 FPGA. The MM-7115’s companion device, the LX160, is Xilinx’s second largest Virtex-4 FPGA with 152,064 logic cells, or 67,584 FPGA slices, that roughly translate to approximately 15 million conventional ASIC gates.

While using RTL abstraction tools such as The MathWork’s Simulink and Xilinx System Generator can reduce development time, resulting compiled VHDL can be verbose and require many more slices than might otherwise be required from hand coded state machines. The LX200 and LX160 counter this concern by providing a large platform that combined offer the equivalent of approximately 35 million ASIC gates.

Virtex-4 Technology
Based on 90nm process technology and the unique column based ASMBL™ architecture, both the LX200 and LX160 provide optimum internal clocking resources. The Virtex-4 Xesium™ clock technology encompasses Digital Clock Manager (DCM) blocks, Phase-Matched Clock Dividers (PMCD), and Differential Global Clocks that ease timing closure and increase performance through the use of independent clock domains.

Reconfigurable Computing
Both the LX200 and the LX160 have additional FPGA platform Flash to store additional bitstreams. This provides customers the ability to load a new bitsream containing a different processing image. With regards reconfiguring the LX160 CoSine Companion Device, because the MM-7115’s principal infrastructure is contained in the LX200 CoSine Primary Device the LX160 can be reconfigured without reconfiguring system interfaces such as the PCI/PCI-X interface, DMA engines, and DDR2 controller.

Rugged Conduction & Convection Cooled Models
The MM-7115 is offered in a rugged convection cooled model (MM-7115DR) and rugged conduction cooled model (MM-7115DT) that each operate at temperatures of -40°C to +71°C. Both models have been designed for optimal heat dissipation and deployment in environments that undergo severe shock and vibration. When fully configured with heat sinks, board stiffeners, and rugged mechanical components, each model is within the space constraints provided by the CMC/PMC draft standard, ANSI/VITA 20-2001 (R2005) for conduction cooled PMCs.