| PowerPC CPUs |
| Device |
Freescale MPC8641D |
| Number of CPU cores |
4 (two per MPC8641D) |
| Speed |
1.0 / 1.25GHz |
| Memory |
2GB DDR2 SDRAM (inc. 8-bit ECC) per MPC8641D |
| FLASH |
512MB (256MB per configuration controller) |
| FPGA Nodes |
| Device |
Xilinx Virtex-5 LX155T or SX95T (speed grade 2) |
| Number of FPGAs |
2 |
| Memory (per FPGA) |
4x 9MB QDR-II SRAM
(18-bit data paths at up to 250MHz)
2x 128MB DDR2 SDRAM
(16-bit data paths at up to 266MHz)
32MB FLASH (for storing FPGA images only) |
| Connectivity |
x8 PCI Express to CPU per FPGA
8x RocketIO per FPGA for VPX (P5)
40 signals between FPGAs (single-ended)
32 LVDS pairs from FPGA0 (VPX P6) |
| Clock References |
See data sheet for details |
| Configuration |
JTAG, MPC8641D and onboard FLASH |
| Ethernet |
| Connectivity |
4x Gbit Ethernet for VPX (P4)
1x Gbit Ethernet in front panel (through optional FTM-01 breakout module) |
| Device |
Embedded within MPC8641D |
| Speed |
1 Gbps |
| Switch |
Provides PowerPC core connection and distributed backplane switching |
| PCI Express |
| Switch Device |
PLX PEX8525 |
| Backplane |
| Compliance |
VPX (VITA 46), VPX REDI (VITA 48) |
| Connectivity |
|
| P0 |
Power, Utility signals (CLK, JTAG, I2C etc.) |
| P1 |
Unused |
| P2 |
Eight PCI Express lanes configured as dual x4 or one x8 link |
| P3 |
Unused |
| P4 |
Four Gbit Ethernet, Four RS-232, Four RS-422/485, external differential oscillator. |
| P5 |
Eight Gbps Transceiver connection to FPGA 0
Eight Gbps Transceiver connection to FPGA 1 |
| P6 |
FPGA User I/O: 32 differential pairs from FPGA 1 |
| FMC Site |
| Compliance |
VITA 57 |
| Software/Firmware |
| Operating System |
VxWorks 6.5, Linux 2.6.x (MPC8641D CPUs) |
| Utilities |
FLASH programming, diagnostics |
| Firmware |
Examples (memory, PCIe, VXS)
FusionXF FPGA Development Resources |
| Miscellaneous |
| Power |
VPX
3.3V (TBA W), 5V (TBA W),
+12V (TBA W), -12V (TBA W) |