| FPGA |
| Device |
Xilinx Virtex-5 LX155T, LX220T, LX330T, SX240T, FX130T and FX200T |
| No. of FPGAs |
2 |
Memory
(per FPGA) |
4x 9MB QDRII SRAM (36-bit data paths at up to 250MHz)
2x 256MB-512MB DDR2 SDRAM (32-bit data paths at up to 267MHz)
16MB FLASH (for storing FPGA images only) |
| Connectivity |
x8 GTP/GTX* RocketIO per FPGA to backplane (P2 & P6) for LX330T/SX240T/FX200T, x4 for LX220T/FX130T
x8 GTP RocketIO between FPGAs for LX330T/SX240T/FX200T, x4 for LX220T/FX130T
x2 GTP/GTX to dedicated FMC site
x2 GTP to FPGA0 from FMC1 (default) or FMC2
x2 GTP to FPGA1 from FMC2 (default)
x4 Serial RapidIO to crossbar switch
38 Single Ended I/Os or 19 Differential Pairs to SCN |
| Configuration |
JTAG, MPC864xD processor, SCN, offboard I/Os and on-board FLASH |
| PowerPC CPUs |
| Device |
Freescale MPC8640D or MPC8641D |
| CPU cores |
2, e600 |
| Speed |
1.0, 1.25 or 1.33GHz |
| Memory |
64KB L1 cache per core, 1MB L2 cache per core (inc. ECC), 512MB-1GB DDR2 per bank |
| FLASH |
128MB, arranged as two 64MB banks or a single 128MB bank |
| NvSRAM |
128KB per MPC864xD with RTC |
| Mezzanine Sites |
| FMC/VITA 57 |
Quad RocketIO x1 and 74 Differential Pairs for LX330T/SX240T/FX200T, 68 for LX220T/FX130T |
| XMC/VITA 42 & 46.9 |
J15 - PCI Express x4/x8 or Serial RapidIO x4
J16 - 38 single-ended I/Os to SCN FPGA
- Up to 16 differential pairs (P3/P4) |
| PMC/IEEE 1386.1 |
PCI (33/66MHz), PCI-X (66/133MHz), 32/64-bit, 3.3V signaling |
| Jn4/VITA 46.9 |
38 single-ended I/Os to the SCN FPGA or
18 Differential pairs and 2 Single Ended I/Os |
| Ethernet |
| Front Panel |
Dual 1000BaseT (front panel RJ45) |
| Backplane |
Dual 1000BaseX to P4 Connector |
| Device |
Embedded within MPC864xD |
| Speed |
10/100/1000Mbps |
| Serial RapidIO |
| Switch Device |
Tundra TSI578 8-port sRIO switch |
| Connectivity |
Both FPGAs, MPC864xD, optional to XMC, four connections to P1 fabric connector, all lanes at 3.125Gb/s |
| PCI Express |
| Connectivity |
Optional to XMC (x4, x8), MPC864xD, Backplane (x8 on P2), all at 2.5Gb/s |
| Serial I/O |
| Device |
DUART embedded within MPC864xD |
| Front Panel |
Dual RS232 |
| Backplane |
Dual RS-232/422 to P4 |
| Backplane |
| Compliance |
VPX (VITA 46) and VPX REDI (VITA 48) |
Connectivity
P0
P1
P2
P3
P4
P5
P6 |
Power and SCN utility signals (I2C)
4 RocketIO x4 to FPGA1
2 RocketIO x4 and x8 PCI Express (optional)
5 Differential pairs from J14, 8 Differential pairs from J16 and 38 Single ended I/Os from SCN
8 Differential pairs from J16, 2 Gbit Ethernet SerDes
Unused
2 RocketIO x4 to FPGA0 |
| Processor Local Bus |
| Connectivity |
32-bit wide connection from CPU to SCN |
| System Control Node |
| Device |
Xilinx Virtex-5 LX70 |
| Connectivity |
32-bit wide connection to MPC864xD
Dual I2C buses
38 single-ended connections to Jn4
38 single-ended connections to Jn6
Up to 38 single-ended connections to P3
38 single-ended connections or 19 differential pairs to FPGA0 and FPGA1 |
| Software/HDL Code |
| Operating System |
VxWorks 6.5, Linux 2.6.x (MPC864xD CPUs) |
| Utilities |
FLASH programming, diagnostics |
| HDL Code |
FusionXF FPGA Development Kit, FusionIPC Development Kit and U-Boot |
| Standards |
| Compliance |
VITA 20, 42.0, 42.2, 42.3, 46.0, 46.3, 46.9, 48 and IEEE 1386 |
| Miscellaneous |
| Power |
VPX
3.3V (TBA W), 5V (TBA W),
+12V (TBA W), -12V (TBA W) |
| Cabling |
Break-out cable with four RS-232 connections, dual Gigabit Ethernet, JTAG & reset button (CABLE-1002) |
| Weight |
TBA |