sFPDP-IP Serial FPDP FPGA IP Core

The VMETRO Serial FPDP-IP (sFPDP) core provides a full specification (ANSI/VITA 17.1-2003) high speed, low latency serial communications link. The serial protocol is derived from the data and control signals of standard (parallel) FPDP (ANSI/VITA 17-1998) and is therefore compatible with this widely used bus system at the transport layer.

One of the main attractions of serializing FPDP links is to overcome the relatively short communication distance limitation (up to about 5m) of the parallel bus. Utilizing VMETRO boards with optical transceiver modules, developers can extend the FPDP range to much greater distances – up to 10km with a single-mode transceiver.

Link Core Architecture
High Speed Serial Transceivers
The core uses one High Speed Serial (HSS) transceiver to create a simple or bi-directional Serial FPDP (sFPDP) interface running at 1.0625Gbps, 2.125Gbps or 2.5Gbps. The transceiver primitive for 8B/10B encoding is used, though the optional cyclic redundancy check (CRC) generation and examination is carried out in the core using an identical encoding scheme and CRC polynomial to that used in Fibre Channel. All link layer operations such as data framing and flow control are implemented in the core.

Frame Assembler/Disassembler
These modules implement the framing protocol. The assembler/disassembler inserts/extracts sFPDP ordered sets.

FIFOs
The transmit and receive path are buffered using FIFOs constructed from FPGA BRAMs (Xilinx Block RAM). The standard FIFOs are asymmetrical in size, where the transmit (Tx) FIFO is 2kbytes and the receive (Rx) FIFO is 8kbytes. The receive FIFO is larger as it must be capable of continuing to store data for twice the time it takes a STOP flow control primitive to reach the data source in the event of a receiver path stall.

Client Interface
The back-end interface to client applications consists of two 36-bit wide ports using the VMETRO Unidirectional Data Stream (UDS) protocol. The ports operate in parallel to support duplex link operation. The lower 32-bits carry data, while the upper 4-bits carry control and status information. This interface can connect directly with the developer’s client application in the FPGA, such as signal processing algorithms. The UDS receiver will continually push data to the back end while there is data in the receive FIFO while the UDS transmitter will continually accept new data as long as there is empty space in the transmit FIFO.

The Control and Status interface is based on dedicated input (control) and output (status) signals. All Link Core control and status signals are active when driven high, including reset.

Clocks
A dedicated clock is needed to drive the transceiver logic. The clock must correspond to the sFPDP link speed. The reference clock is usually 1/20th of the link speed. When running the core at the highest link speed of 2.5Gbps, the RocketIO™ reference clock is taken from the dedicated clock pins (BREFCLK/BREFCLK2) to minimize clock jitter. A user clock is used for the back end client UDS interface and may be asynchronous to the transceiver logic clock.

Development Toolchain

Simulation: ModelSim or other standard VHDL simulators can be used, though a SWIFT licence is also required for the simulation of HSS transceiver primitives. The IP is supplied in obfuscated code or full VHDL source.

sFPDP Configurations
sFPDP is a data streaming protocol, rather than a network protocol. Therefore the protocol header does not provide for node identification or addressing. Instead, a sFPDP connection provides a link from the source interface to its destination(s). A return link can also optionally be provided.