FAQ for Vanguard Analyzers & Exercisers



GENERAL

Q:  What is the minimum clock frequency supported by the Vanguard?

Q:  What is the maximum clock frequency supported by the Vanguard?

Q:  When in master mode and for both reads & writes, how many clock cycles are there between FRAME and IRDY? When transfer is complete, what's the minimum number of clock cycles between FRAME deasserted and reasserted (i.e. how fast can the card issue another transaction once a previous one is complete)?

Q:  If BusView is running on both the system under test and on the control system, will there be conflicts?

Q:  Is there a user-friendly way to display the bus, device, function, and byte count for each transaction?

Q:  Is there a way not to accidentally lose an already captured trace after clicking on Analyzer/Run (like a pop-up window that signals that the captured trace has not been saved and will therefore be lost if the user continues) ? 

Q:  How do I sample at power up?

 

INSTALLATION, HW & COMPATIBILITY

Q:  The BusView software asks for a software license key.  Where is this found?

Q:  The Vanguard PCI Analyzer will not plug into the backplane.

Q:  Using the Vanguard PMC, the DUT will not power up.

Q:  Using the Vanguard PCI, PMC or cPCI in a custom slot, the Vanguard is reporting "Undefined Bus".

Q:  Using the Vanguard analyzers, is it okay to use a non-VMETRO power supply?

 

COMMUNICATION, FIRMWARE UPLOADS, ETC.

Q:  How do I connect to the analyzer over the Ethernet using a specified static IP address?

Q:  Using the Vanguard PCI, PMC, cPCI, or VME, the card cannot see the USB connection in Windows 2000.

Q:  What's the cause of UNKN/33M3 flashing on the LED display?

Q:  Using the Vanguard PCI, cPCI or VME, the "WAIT" message at front panel of board stays on. It is not able to establish connection to the Host PC.

Q:  BusView no longer finds the Vanguard hardware when it does a scan, the board displays "LOAD" then shows the bus frequency and all 4 front panel LEDs remain on.

Q:  Using the Vanguard PCI, PMC or cPCI, the card is not reporting a clock.

 

ANALYZER FUNCTIONALITY

Q:  Using the Vanguard PCI, PMC, or cPCI, when switching modes, the bus frequency will not change when switching from PCI to PCI-X.

Q:  Our bus runs at 100 MHz. How can I change the bus mode for the Vanguard to run at 100 MHz also?

Q:  Is there a way to prevent the Vanguard analyzer from requesting the REQ and GNT lines?

Q:  How do I "search" for a transaction in a trace like "Memory Read that finished with a split completion, Like a sequencer type capability?

Q:  What is the sequence to use for filtering out all data phases during acquisition?

Q:  How do I display the M66EN & PCIXCAP signals with the others on the logic analyzer?

Q:  Is it possible to redefine the name of the fields in the analyzer trace window display, e.g. renaming FRAME# ->F#, REQ64# ->Q64#, etc.?

 

EXERCISER FUNCTIONALITY

Q:  Can the user make the exerciser generate weird cycles, have flexibility on the way some signals are driven by the exerciser on the bus so as to reproduce bugs, test root cause theories on some bugs, etc. (e.g. have the CBEs toggle during data block transfers)?

Q:  Can the user program the number of clock cycles between signals for the exerciser, for instance between FRAME and DEVSEL/IRDY in target mode, between FRAME & TRDY in master mode, etc.?

Q:  When in target mode, how many clock cycles are there between FRAME and the card replying with DEVSEL, and between IRDY and TRDY?

Q:  When doing reads with the exerciser, are we guaranteed that the returned values are always correct whatever the platform behavior (RETRY, SPLIT COMPLETION, or ten retries in a row)? How does the tool behave if it receives retry or split completion? Does it retry or will it go into a wait state, etc.?

Q:  Using the Vanguard PCI or cPCI, the Exerciser does not come up with a prompt.

Q:  Using the Vanguard PMC, the Exerciser does not come up with a prompt.

Q:  Why can I still choose the option for Exerciser capabilities even though they were not purchased, ?

Q:  Using the Vanguard PCI, PMC or cPCI, with the Exerciser, is it possible to enter a 64-bit address?

Q:  When the exerciser is a target, is it possible to program its behavior in response to requests on the bus, like reply with 3 retries on all MemReads, reply with split completion on MemWriteBlocks, etc.?

Q:  Does the exerciser have the capability of generating outstanding transactions (like MemRdBlocks), and if so, how many?

Q:  What is the tool's max sustained ReadBlock & WriteBlock over a second or 1 MB to/from host memory (assuming the system is not a bottleneck)?

Q:  Are the starting and ending addresses in the test tab of the exerciser an absolute or relative (add 0 is starting range of memory assigned) memory value?

Q:  If you want to exercise with 3 clk cycles between FRAME and IRDY, is this possible?

 

GENERAL


Q: What is the minimum clock frequency supported by the Vanguard?
A: The Vanguard supports PCI and PCI-X clock frequencies down to 1 KHz. A low frequency set of firmware images must be loaded prior to operation below 30 MHz. Please refer to the BusView manual for further details.


Q:  What is the maximum clock frequency supported by the Vanguard?

A: The Vanguard supports PCI and PCI-X clock frequencies down to 1 KHz. A low frequency set of firmware images must be
loaded prior to operation below 30 MHz. Please refer to the BusView manual for further details.


Q:  When in master mode and for both reads & writes, how many clock cycles are there between FRAME and IRDY? When transfer is complete, what's the minimum number of clock cycles between FRAME deasserted and reasserted (i.e. how fast can the card issue another transaction once a previous one is complete)?
A:  For reads and writes, IRDY is asserted on the second clock after the attribute phase. This is 3 clocks after Frame.


Q:  If BusView is running on both the system under test and on the control system, will there be conflicts?
A:  There will be no conflicts. Only one system can connect with the analyzer at a time. Connection is only via Ethernet or USB for either system.


Q:  Is there a user-friendly way to display the bus, device, function, and byte count for each transaction?
A:  The BusView GUI displays this information by the user sliding the cursor over the Requester ID and the Completer ID fields in the Trace Display.


Q:  Is there a way not to accidentally lose an already captured trace after clicking on Analyzer/Run (like a pop-up window that signals that the captured trace has not been saved and will therefore be lost if the user continues) ? 
A:  There is no option for this request.  If there is a trace that you don’t want to lose, you will have to save it.


Q:  How do I sample at power up?
A:  By using an emulator VT100 or HyperTerminal and turning on the save trace options under Trace->Save Trace Options and making your selection. The Analyzer then samples at power-up. This option is not available in BusView and the Vanguard does not offer this functionality. Alternatively, carry out a warm boot by setting the analyzer to trigger on reset deassert.

 

INSTALLATION, HW & COMPATIBILITY


Q:  The BusView software asks for a software license key.  Where is this found?
A:  The license key is located on the back of the BusView CD Case that is included with the board.  This is inserted in the lid of the box. If you have lost the license key, you may request a new key from VMETRO support.


Q:  The Vanguard PCI Analyzer will not plug into the backplane.
A:   If the backplane has 5V slots, the 5V adapter is needed for the analyzer to be plugged into the slot.  The Vanguard PCI is a 3.3V only device. The 5V adapter is included with the analyzer.


Q:  Using the Vanguard PMC, the DUT will not power up.
A:  Make sure the carrier board delivers both 3.3V power and 5V power.  This is regardless of whether the analyzer uses External Power.  The top spacer requires both in order to connect the DUT. If your system does not provide either 3.3V or 5V, contact VMETRO for a custom top spacer card to work around this problem.


Q:  Using the Vanguard PCI, PMC or cPCI in a custom slot, the Vanguard is reporting "Undefined Bus".
A:  When using external power, a PCI reset has to be issued after the system is powered to detect the correct bus mode and frequency.


Q:  Using the Vanguard analyzers, is it okay to use a non-VMETRO power supply?

A: The Vanguard is very sensitive to low voltage conditions. We offer an external power supply which is suitable: Part Number 401-VG-EPSU. VMETRO does not recommend using a generic power supply. The VMETRO power supply has current and voltage sense at the connector to ensure reliable operation under changing conditions.

 

COMMUNICATION, FIRMWARE UPLOADS, ETC.


Q:  How do I connect to the analyzer over the Ethernet using a specified static IP address?
A:  The IP address must be on the same subnet as the BusView Host PC. For example if the IP address assigned to the PC is 192.168.253.100, the IP address for the analyzer must be 192.168.253.x where x is a number from 0 to 254. The first three digits MUST be the same. If not, the two devices will not see each other. To assign a static IP for Vanguard, you should carry out the following procedure:

  1. Connect to the analyzer with USB.
  2. At the DOS/Command prompt of the BusView PC, type IPCONFIG to display what the IP address is currently set to.
  3. Determine an IP address that is secure within the same subnet as the PC.
  4. To test if this IP address has already been used, still at the Command prompt, type ping <IP Address>. If the request times out then this is a good IP address. If there is a response, then the IP address is already in use and another address must be chosen. Go back to step 3.
  5. Close the command Window and open the Hardware Connection dialog box in BusView.
  6. Enter the IP address chosen for the Vanguard in the Advanced tab.
  7. Go to the devices window and connect to the board.


Q:  Using the Vanguard PCI, PMC, cPCI, or VME, the card cannot see the USB connection in Windows 2000.
A:  Unfortunately this is a known issue with Windows 2000 and USB. There is no known fix for it. There are three possible remedies:

  1. Before rebooting, always select "Disconnect" in BusView and disconnect the USB cable.
  2. Switch to using Ethernet instead of USB.
  3. Use a PC with Windows XP.

Q:  What's the cause of UNKN/33M3 flashing on the LED display?
A:  The analyzer is not able to determine whether the bus mode is PCI or PCI-X. This means that the analyzer did not see a PCI Reset on the bus. Assert PCI Reset and the bus will go from Unknown to PCI or PCI-X.


Q:  Using the Vanguard PCI, cPCI or VME, the "WAIT" message at front panel of board stays on. It is not able to establish connection to the Host PC.
A: Check the yellow and orange color LED under the reset switch of the front panel. If they are lit, the analyzer is expecting a FW upload. This is caused by incorrect setting of the DIP switch 2 number 4 (SW2 switch 4 set to ON). To complete the procedure, do the following:

  1. Power off the Vanguard
  2. In BusView, go to Tools->Hardware->Firmware Watchdog->Enable
  3. Power on the Vanguard while connected on Ethernet
  4. Wait for the firmware upload to complete
  5. Power down the Vanguard
  6. Set SW2 switch 4 to OFF
  7. Power the Vanguard back on.

Q:  BusView no longer finds the Vanguard hardware when it does a scan, the board displays "LOAD" then shows the bus frequency and all 4 front panel LEDs remain on.
A:  The most probable cause of this is insufficient power supply. If the supply voltage drops below 3.25V, you may experience unstable operation.  Measure the 3.3V power supplied to the board. If it is below 3.3V, using the Vanguard external power supply may solve the problem.


Q:  Using the Vanguard PCI, PMC or cPCI, the card is not reporting a clock.
A:  Check to make sure that "No Exerciser" is NOT selected.  To save power, some systems will turn off the PCI clock to a slot where it does not detect a card. When the Vanguard is set to "No Exerciser", the system will not be able to detect it, and consequently will treat the slot as not in use and shut off the clock.

 

 

ANALYZER FUNCTIONALITY


Q:  Using the Vanguard PCI, PMC, or cPCI, when switching modes, the bus frequency will not change when switching from PCI to PCI-X.
A:  From the BusView GUI, under Tools->Hardware->Options, make sure that the correct options are selected for Bus Mode and PCI Clock Frequency. After the correct selections have been made, be sure to issue a PCI reset.


Q:  Our bus runs at 100 MHz. How can I change the bus mode for the Vanguard to run at 100 MHz also?
A:  The Vanguard does not set the frequency, the system does. Select Tools->Hardware->Options->Exerciser Functions Bus Mode. In this menu you must select the 133 MHz clock frequency option to get 100 MHz. You must issue a PCI reset for this to take effect.


Q:  Is there a way to prevent the Vanguard analyzer from requesting the REQ and GNT lines?
A:  Set the Exerciser Mode to "No Exerciser" in Tools->Hardware->Options.


Q:  How do I "search" for a transaction in a trace like "Memory Read that finished with a split completion, Like a sequencer type capability?
A:  The Search feature has the capability to search forward in the trace buffer for the corresponding Completion if it was captured.


Q:  What is the sequence to use for filtering out all data phases during acquisition?
A:  In transfer mode, use an event where the Transfer Column is set to Start. In Standard and Clock mode, set the State column to Addr.


Q:  How do I display the M66EN & PCIXCAP signals with the others on the logic analyzer?
A:  These are static signals and do not change. The analyzer does not have specific pins for these, but you can use one of the 16 external inputs for these. The External Inputs can also be renamed so that the signals are easier to differentiate.


Q:  Is it possible to redefine the name of the fields in the analyzer trace window display, e.g. renaming FRAME# --> F#, REQ64# --> Q64#, etc.?
A:  It is not possible to change these names but you can change the size of the column by clicking and dragging. You can also remove unwanted columns and fields from the trace display.

 

 

EXERCISER FUNCTIONALITY


Q:  Can the user make the exerciser generate weird cycles, have flexibility on the way some signals are driven by the exerciser on the bus so as to reproduce bugs, test root cause theories on some bugs, etc. (e.g. have the CBEs toggle during data block transfers)?
A:  No, this is not supported. In PCI-X mode, the E2 Exerciser can generate Parity Errors and other errors, but it can not change signal timing.


Q:  Can the user program the number of clock cycles between signals for the exerciser, for instance between FRAME and DEVSEL/IRDY in target mode, between FRAME & TRDY in master mode, etc.?
A:  No, the signal timing can not be changed.


Q:  When in target mode, how many clock cycles are there between FRAME and the card replying with DEVSEL, and between IRDY and TRDY?
A:  DEVSEL is asserted on the second clock after the attribute phase.  IRDY# to TRDY# is 4 to 6 clocks depending on the command and on whether a split response is issued or not. The E2 Exerciser has programmable decode speed. B, C, 5, Subtractive and 7 are supported.


Q:  When doing reads with the exerciser, are we guaranteed that the returned values are always correct whatever the platform behavior (RETRY, SPLIT COMPLETION, or ten retries in a row)? How does the tool behave if it receives retry or split completion? Does it retry or will it go into a wait state, etc.?
A:  Yes, as long as the response is compliant with the specification, the displayed data will be correct.


Q:  Using the Vanguard PCI or cPCI, the Exerciser does not come up with a prompt.
A:  From the BusView GUI, under Tools->Hardware->Options, make sure that the Exerciser option is selected, the Analyzer has seen a PCI Reset, the System Arbiter is functional, and that Busview reports a clock on the bottom of the screen.


Q:  Using the Vanguard PMC, the Exerciser does not come up with a prompt.
A:  When using the Top Spacer with a DUT, make sure that the jumper is in the Secondary position and that the motherboard has PrPMC capabilities (please see App note on using the Vanguard in custom and embedded environments).  Also, make sure that the Analyzer has seen a PCI Reset, the System Arbiter is functional and that the Analyzer reports a clock.


Q:  Why can I still choose the option for Exerciser capabilities even though they were not purchased, ?
A:  In some systems, the Exerciser has to be enabled to prevent the system from turning off the clock.  The exerciser will be detected by the system BIOS.  This will be the only function that the Exerciser is used for if the Exerciser capabilities are not purchased.


Q:  Using the Vanguard PCI, PMC or cPCI, with the Exerciser, is it possible to enter a 64-bit address?
A:  The PCI exerciser does not support 64-bit addressing (i.e. Dual Address Cycles – DAC), only 64-bit data. The PCI-X exerciser supports both 64-bit addressing (using DAC) and 64-bit data.


Q:  When the exerciser is a target, is it possible to program its behavior in response to requests on the bus, like reply with 3 retries on all MemReads, reply with split completion on MemWriteBlocks, etc.?
A:  In PCI-X mode, the exerciser can be programmed to do a specific termination. However, it can not be programmed to do a set amount of retries before delivering the data or change Target Termination after a set amount of accesses. No such programming is available in PCI mode.


Q:  Does the exerciser have the capability of generating outstanding transactions (like MemRdBlocks), and if so, how many?
A:  The target can not be programmed to withhold completions. As a Master, it is capable of holding 32 outstanding transactions if the target does not return the completion right away.


Q:  What is the tool's max sustained ReadBlock & WriteBlock over a second or 1 MB to/from host memory (assuming the system is not a bottleneck)?
A:  DMA Read Performance 133 MHz PCI-X 64 bit Data =  864 MB/s 
DMA Write  Performance 133 MHz PCI-X 64 bit Data = 949 MB/s.
This test was done Vanguard to Vanguard so these numbers are valid for both Target and Initiator.


Q:  Are the starting and ending addresses in the test tab of the exerciser an absolute or relative (add 0 is starting range of memory assigned) memory value?
A:  Only Absolute addresses are used in the Exerciser menus. This address is the PCI address of the device being tested.


Q: If you want to exercise with 3 clk cycles between FRAME and IRDY, is this possible?
A: You can not change the timing of signals, but since this is the timing used by the exerciser, it is possible.