PMC-FPGA02 Xilinx Virtex II FPGA PMC

The PMC-FPGA02 is a 64-bit/66MHz PMC format high-speed digital I/O module using a Xilinx™ Virtex-II FPGA. I/O is customizable through an I/O adapter. 128Mbytes of SDRAM is provided for local data buffers.

Xilinx Virtex FPGA
A Xilinx XC2V3000 or XC2V6000 FPGA is provided as standard build options - 8 million gate XC2V8000s are available on request. The FPGA can be configured via a remote host across the PCI interface. Alternatively, the PMC-FPGA02 can be set to configure from the flash memory. The 4Mbyte flash memory can store up to three configurations.

The FPGA02 also includes 12Mbytes of Quad Data Rate (QDR) SRAM. Due to the flexibility of the FPGA  it can be used as standard SRAM or even FIFOs - ideal for storing intermediate data created by algorithms running the FPGA.

Digital I/O with LVDS and FPDP I/O
LVDS (or single-ended e.g. LVTTL) signals are routed to the front panel and the P14 user I/O connector (user configurable).

Routed to a header, just behind the front panel, are 69 signals from the FPGA. An I/O adapter module can be plugged onto this header and provides the appropriate external connector. Another 64 lines are routed to the PMC user I/O connector P14 (P2). PMC hosts, such as VME SBC boards, can make use of these signals directly with backplane I/O.

Adapter modules to enable the use of FPDP are also available. Users can create their own custom I/O adapter modules to suit their own particular I/O needs and available I/O FPGA IP cores.

Software
Most of the FPGA is left free for user applications. To aid FPGA configuration, example VHDL library code blocks are provided to show how the PMC-FPGA02 resources can be used. Flash programming utilities are also provided.

For the PMC host, a board support package is provided with C++ libraries for controlling DMA transfers and interrupts handling.

Development of VHDL code for the FPGA requires synthesis tools such as Xilinx Foundation.