How do the Phoenix VPF1s PowerPC CPUs communicate with the FPGAs?
In what way are QDR SRAMs useful?
How fast are the QDR SRAM memories?
Am I free to determine how the QDR SRAM is used?
How fast can the serial communications operate?
Can I use protocols such as Serial RapidIO, Infiniband, PCI-express?
What if I need higher speed communications within my system?
Do I need a special VME backplane to use the VPF1?
What FPGA development tools do I require?
What is the power consumption and weight of the Phoenix VPF1?
What software support is supplied and what operating systems are supported?
Q: How do the Phoenix VPF1's PowerPC CPUs communicate with the FPGAs?
A: Each PowerPC 7447 processing node is coupled to its own Marvell MV64360 bridge, giving it access to an array of communications resources. These include a 64-bit, 125MHz PCI-X bus used exclusively for high-bandwidth FPGA communications and a low latency point-to-point datalink. This is backed-up by a 32-bit device bus. Firmware is provided which enables the PCI-X bus to be used as multiple (virtual) channels; as far as software is concerned, there are several separate links mirroring the FPGA's serial communications.
Q: How is the FPGA configured?
A: The FPGA can be configured in three ways: from FLASH during power up, under host processor control or via JTAG. Each of the Phoenix VPF1's FPGA node configuration files is supplied by its adjacent PowerPC processor: the configuration is stored in the PowerPC CPU's FLASH. VMETRO development tools facilitate configuring the FPGA in both development and run-time environments. JTAG can also be used for FPGA configuration during development. An onboard battery (optional) is available so that encrypted keys can be stored for secure FPGA configurations.
Q: In what way are QDR SRAMs useful?
A: Fast banks of SRAM are ideal for lookup tables, local data buffers and DSP operations such as dealing with concurrent Multiply- ACcumulate (MAC) data streams. Although FPGAs include an amount of on-chip memory, this is not sufficient for applications that need to support large datasets, such as large FFTs, or framestores for image processing. Without external memories, the operational performance could be severely compromised or it may even be impossible to implement the algorithm.
Each VPF1 FPGA node includes four banks of 2M x 18-bit QDR SRAM.
Q: How fast are the QDR SRAM memories?
A: Each of the four independent QDR memories is clocked at 125MHz. QDR devices have discrete double data rate (DDR) read and write ports, both of which operate simultaneously. The ports are 18 bits wide and latch data on both the rising and falling edges of the clock, so there is a potential 4.5Gbit/sec read + 4.5Gbit/sec write per device when all bits are used. This equates to a total bandwidth of 1.125Gbytes/sec for 18 bit data, or 1.000Gbytes/sec for 16 bit data.
Q: Am I free to determine how the QDR SRAM is used?
A: Yes.
The QDR SRAM memory devices are directly linked to control blocks implemented in the FPGAs; they are not on a shared bus. This means that each QDR memory bank is not restricted in how it can be used to perform functions such as synthesizing FIFOs, linear-addressable memory pools, bit-reversed addressing or circular buffers – which can be done as best suits the application.
Q: How fast can the serial communications operate?
A: The Virtex-II Pro FPGAs feature 2.0/3.125Gbps RocketIO™ transceivers. Four RocketIO channels connect the two FPGA nodes and four channels from each FPGA are available for off-board communications. The ability of the FPGA to generate 2.0 or 3.125Gbps data streams is dependent on the speed grade of the FPGA (–5 & –6 speed grade, respectively), which is a build option. Note that multiple RocketIOs from a single device can be ‘bonded’ together to synthesize higher bandwidth data links.
Q: Can I use protocols such as Serial RapidIO, Infiniband, PCI-express?
A: Yes, but these require FPGA firmware IP cores to handle the dataflow and protocol layers; the RocketIO transceivers already provide the electrical interfaces and physical layers. The embedded RocketIO multi–gigabit transceivers are designed to operate at any baud rate in the range of 622 Mbps to 3.125 Gbps per channel. This includes specific baud rates used by various serial standards such as Serial RapidIO, Infiniband, Fibre Channel, PCI–X and Gigabit Ethernet. Implementation of these protocols is reliant on configuring the FPGA to control the dataflow accordingly, either with self-developed or purchased IP cores. Higher level control, such as protocol stacks, can be accomplished using the embedded PowerPC 405 processors in the Virtex–II Pro. Cores for 1 Gb Ethernet MAC with PHY, 10 Gb Ethernet MAC with XAUI, PCI Express, Serial RapidIO, Fibre Channel, and reference designs for SONET OC–48 backplanes are available from Xilinx and more are being added.
Q: What if I need more than 3.125Gbps serial data links?
A: RocketIO serial communications channels can be bonded together. For example, four 2.0 Gbps data links can be operated as a single 8.0 Gbps data link. Four RocketIO channels connect the two VPF1 FPGA nodes and four channels from each FPGA are available for off-board communications. Some gigabit I/O standards (such as Infiniband) specify the use of multiple transceivers in parallel to synthesize even higher data rates. Data words are split into bytes, with each byte sent over a separate transceiver channel. These data bytes are then reconstructed, in order, at the receiver. To support correction of any data misalignment, the data stream includes special byte sequences that define corresponding points in the several channels.
Q: Do I need a special VME backplane to use the VPF1?
A: No. The Phoenix VPF1 is VITA 41 VXS compliant card which means that it is essentially a VME64x card. However, in order to achieve the Gigabit speed data links, the VXS P0 connector is a MultiGig (RT2) type connector with balanced differential signal routing and ground planes. This connector is not compatible with the standard VME P0 connector which is incapable of handling the necessary bandwidth, so high-speed off-board communications does require a VXS backplane. This also means that the card will not fit into a backplane with a standard P0 or other obstruction in that area.
Note that, conversely, a standard VME card that does not have a P0 connector (or other obstruction) will fit into a VXS backplane.
Q: What is VXS?
A: VME Switched Serial Extensions (VITA 41, also known as VXS), defines a superset of functionality over the VME bus standard to include multi-Gbps switched serial interconnect(s) across the backplane.
To prevent the specification becoming tied to a dead–end technology, it specifies the use of open standard technology for the multi–Gbps serial switched links and is able to accommodate different link technology standards; though not necessarily at the same time. VXS also supplies additional D.C. power onto each VME card while maintaining backward compatibility with the VMEbus legacy.
Q: What FPGA development tools do I require?
A: VMETRO supply firmware reference designs to support all on–board hardware to which the FPGA has access. In order to develop from these reference designs and generate their own configuration files, the user will need a logic design toolchain. The latest Xilinx ISE toolchain is used by VMETRO to develop support and example firmware. ISE provides integration with the leading 3rd party synthesis engines from Mentor Graphics, Synopsys, and Synplicity. However, VMETRO have used the Xilinx proprietary synthesis technology XST (which is provided as part of ISE) for the synthesis stage of each library design.
Q: What is the power consumption and weight of the Phoenix VPF1?
A: The VPF1 weighs:
| VPF1 conduction cooled | 1.89 lbs. (857.3g) |
| VPF1 air cooled | 1.98 lbs. (898.2g) |
The VPF1 power figures are:
|
FPGA power (each) |
5V current |
3.3V current |
Board power dissipation |
|
10W |
9.4A |
8.2A |
74W |
|
15W |
9.4A |
11.6A |
85W |
|
20W |
9.4A |
15.1A |
97W |
Q: What software support is supplied and what operating systems are supported?
A: Software development is supported using the most common compilers for the operating system platform. This is Microsoft Visual C++ for Microsoft platforms and the GNU compiler for VxWorks, Linux and LynxOS. The initial operating system support for the VPF1 includes Linux and VxWorks (Tornado 2.2).
A BSP library provides integration support. It is a C++ library supporting general hardware access and the implementation of high-speed DMA and switched packet serial communications routines. Full source code for the libraries is supplied. Example programs using these library routines are included to perform such tasks as setting up various DMAs to and from the board, including 'continuous mode' DMAs, using the QDR SRAM and how the board handles interrupts.
Runtime application development is supported by third party libraries such as the MPI VSIPL library providing a core set of DSP functions optimised for the PowerPC 74xx (AltiVec) processor.
Host utilities are provided to give the user a graphical user interface with a complete view of the board hardware (registers, memory etc.). Other utilities allow for system evaluation and functional testing, as well as configuring the FPGA from the host and loading the FLASH.
Support Summary:
Operating Systems
- VxWorks
- Linux
Libraries
- VSIPL
- Board support
Communications Libraries
- MPI (under linux – planned)
- TransComm™ – Memory mapped processor to processor nodes, boards to board links, Ethernet, switched serial I/O
Diagnostics
- System probe/diagnostic
- Built-In Test (BIT)
- JTAG
Utilities
- Flash programming
- FPGA configuration
- Drivers & integration support for third party I/O cards