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Embedded Computing -
Data Recording & Storage -
Protocol & Bus Analyzers
Related Products:
- PMC-FPGA05 - User Programmable Virtex-5 LX110 FPGA PMC module with plug-in I/O Adapter Modules
- DEV-FPGA05 - User Programmable Virtex-5 LX110 PCI board with plug-in I/O Adapter Modules
- PMC-FPGA03 - User Programmable Virtex II Pro based FPGA PMC module
LVDS-MOD3
- 64 I/O lines routed as 32 differential pairs
- 68-way SCSI-3 style front panel connector
- Mixed voltage signalling
- FPGA Firmware blocks supplied in VHDL for integration into user applications
- Windows, VxWorks and Linux host PMC support
The LVDS-MOD3 is a front panel mezzanine module designed to provide LVDS I/O functionality to VMETRO's FPGA-based processing PMC modules. This module provides 32 differential pairs to the front panel. The LVDS-MOD3 is aimed at embedded application development.
The LVDS-MOD3 is designed to be used with:
| - PMC-FPGA05 | A Virtex-5 LX110 FPGA based PMC |
| - DEV-FPGA05 |
A Virtex-5 LX110 FPGA based PCI board |
| - PMC-FPGA03 |
A Virtex II Pro XC2VP50 FPGA based PMC |
Low Voltage Differential Signaling Module (LVDS-MOD3)
The LVDS-MOD3 is a transition module designed to passively route I/O signals from the VMETRO FPGA PMC module's high density connector to a standard 68-way SCSI-3 style front panel connector.
LVDS Signaling
Sixty four I/O lines are routed as 32 length-matched differential pairs with 100 Ohm impedance traces, supporting the module's primary role of high-speed LVDS signalling. There are no termination resistors on the LVDS-MOD3 as the FPGA on the PMC module provides LVDS terminations at the receive buffers.
Single End Signalling
The PMC module provides signals to the LVDS-MOD3 module from two separate banks of the FPGA. The user can independently control the power rail for each of these two banks, allowing a mixture of 2.5V and 3.3V signalling to be used on both input and output signals. Table 1 shows the number of signals per bank.
Table 1
| FPGA Bank | No. IO lines | No. LVDS pairs |
| 0 | 36 | 18 |
| 1 | 29 | 14 |
5V Signalling
The LVDS-MOD3 provides a single, bi-directional 5V tolerant signal line.
Global Clock Inputs
The LVDS-MOD3 provides 4 (2 pairs) global clock inputs at the front panel. One pair connects to bank 0 of the FPGA while the other connects to bank 1. It is possible to route another two pairs to the front panel, though this requires a specific build of the PMC module. Contact VMETRO support for further information.
Software
The LVDS-MOD3 is hosted by the PMC-FPGA03, PMC-FPGA05 or DEV-FPGA05 which are supported under Windows XP, VxWorks and Linux (Contact VMETRO for availability). The LVDS-MOD3 support package is additional to the BSP that accompanies VMETRO PMC modules and includes:
VHDL library code blocks: demonstrating how board resources can be used and how Signaling operations are controlled by the host FPGA
Hardware and firmware/software manuals
Development of VHDL code for the FPGA requires synthesis tools such as Xilinx Foundation.
