TS-C43 Quad ADSP-TS101 PMC with FPGA I/O

The TS-C43 is a quad (clustered) ADSP-TS101 DSP PMC format module with a Xilinx Virtex-II FPGA co-processor and high-speed digital I/O port. This makes the TS-C43 ideal for radar, sonar and telecommunications applications. The PCI interface supports 64-bit/66MHz operations.

Multi-TigerSHARC DSP Architecture
Like SHARC DSPs the TigerSHARC DSP has dedicated inter-DSP communications links known as link ports. Each TigerSHARC DSP has four such links and enables the DSPs to have optimal datapaths to best suite differing applications. The TS-C43 has a fully connected TigerSHARC DSP topology with each DSP connected to all other DSPs. One link port from each DSP is also available off-board via the FPGA. The FPGA provides link to the user I/O connector.

User FPGA
A Xilinx XC2V1000-5 Virtex-II FPGA is available as standard for both user I/O and a co-processor for accelerating applications such as Viterbi decoding. The FPGA provides two 64-bit independent data paths (69 to the front panel and 64 for user I/O). As the FPGA can be used to handle the interface protocol, the mezzanine often only needs a front panel connector and line drivers - sometimes little more than the connector is required. This allows for fast design turnaround at low cost. These modules can provide interfaces including camera link or simple parallel ports. Direct support from VMETRO includes FPDP and SERDES modules together with example code for receive and transmit modes. The FPGA shares the bus with the TigerSHARC DSPs and so has access to the full bus bandwidth and board's resources.