TS-V39 Octal ADSP-TS101 VME with FPGA I/O

The TS-V39 is an quad/octal ADSP-TS101 DSP (TigerSHARC) VME format board arranged in two clusters of four DSPs. Each cluster's resource includes a Xilinx Virtex-II FPGA, 256MB SDRAM and flash memory.

The TS-V39 offers the maximum TigerSHARC DSP processor density and scalability: ideal for radar, sonar and telecommunications applications.

Flexible Multi-TigerSHARC DSP Architecture
The TigerSHARC DSP has dedicated inter-DSP data communications channels known as link ports. Each TigerSHARC DSP has four such links enabling the DSPs to have the optimal data paths for the application. These include pipelines, two-dimensional arrays and hyper-cubes.

User FPGAs
A Xilinx XC2V1000-5 Virtex-II FPGA on each cluster is available to accelerate applications such as Viterbi decoding. Each FPGA shares the local bus with a TigerSHARC DSP cluster and so has access to the full bus bandwidth and other cluster resources.

FPGA Based Digital I/O
For high-speed digital I/O each of the FPGA signals are routed to a header onto which a mezzanine can then be fitted. Since the FPGA can be used to handle the interface protocol, the mezzanine often only needs a front panel connector and line drivers - sometime little more than the connector is required. This allows for fast design turnaround at low cost. These modules can provide interfaces including multiple SPORTs, camera link or simple parallel ports. Direct support from VMETRO includes FPDP and LVDS together with example code for receive and transmit modes.

The TS-V39 is part of VMETRO's TigerSHARC DSP based product family which includes PCI, compactPCI and PMC members.