TS-CP39 Octal ADSP-TS101 cPCI with FPGA I/O

The TS-CP39 is an octal ADSP-TS101 DSP (TigerSHARC) CompactPCI format board arranged in two clusters of four DSPs. Each cluster has a Xilinx VirtexT-II FPGA, SDRAM and flash memory. The TS-CP39 offers the maximum TigerSHARC DSP processor density and scalability: ideal for ideal for radar, sonar and telecommunications applications.

Flexible Multi-TigerSHARC DSP Architecture
The TigerSHARC DSP has dedicated inter-DSP data communications channels known as link ports. Each TigerSHARC DSP has four such links enabling the DSPs to have the optimal data paths for the application. These include pipelines, two-dimensional arrays and hyper-cubes.

User FPGAs
A Xilinx Virtex-II XC2V1000-5 FPGA is provided as standard for each cluster to accelerate applications such as Reed-Soloman decoding. Each FPGA shares the local bus with a TigerSHARC DSP cluster and so has access to the full bus bandwidth and cluster resources.

FPGA Based Digital I/O
For high-speed digital I/O, 64 signal from each of the FPGAs are routed to a header onto which a mezzanine can then be fitted. Since the FPGA can be used to handle the interface protocol, the mezzanine often only needs a front panel connector and line drivers - sometime little more than the connector is required. This allows for fast design turnaround at low cost. These modules can provide interfaces including camera link or simple parallel ports. Direct support from VMETRO includes FPDP together with example code for receive and transmit modes.

The TS-CP39 is part of VMETRO's TigerSHARC DSP based product family that includes PCI, VME and PMC members.