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Embedded Computing -
Data Recording & Storage -
Protocol & Bus Analyzers
Related Products:
- PMC-FPGA03F - User Programmable Virtex II Pro FPGA PMC module with Quad Fiber-Optic Transceivers
- PMC-FPGA03 - User Programmable Virtex II Pro based FPGA PMC module
- PMC-FPGA02 - Xilinx Virtex II FPGA PMC
- PMC-FPGA01 - Xilinx Virtex-E FPGA PMC
- TS-C43 - Quad ADSP-TS101 PMC with FPGA I/O
TPMB2
- 2 PMC Sites
- 64-bit/66MHz PCI
- Third PMC Site for Development
- 64-bit PCI-PCI Bridge
- CompactPCI Test Site
- VME P2 Compatible PMC I/O
- Standalone Mode
- Twin Fans for PMC Cooling
- JTAG Header
The TPMB2's architecture provides up to three PMC sites on a 64-bit PCI card isolated by a PCI-PCI bridge device. The use of a bridge ensures that the TPMB2 is fully PCI 2.2 compliant. As such, the TPMB2 is a low cost solution for developing and testing PMC modules.
64-bit PCI Interface
Throughout the system, a 64-bit/66MHz PCI backbone is used. The PCI bus is connected to a PCI backplane using an HiNT HB2 PCI-PCI bridge. The TPMB2 can be used in a 32-bit or 64-bit backplanes as required by PCI 2.2.
CompactPCI Test Site
In addition to PMC modules, compactPCI cards can be developed without a compactPCI backplane, but using the TPMB2 instead. This is done by providing a PCI bus connection up to a compactPCI connector on the top edge of the TPMB2. This reduces the need for expensive compactPCI backplanes for single board developments. This is a build option.
Third PMC Site
On the reverse side of the TPMB2 is a third PMC site. Intended to provide maximum access to PMC development, this site is mounted at a right-angle to the normal PMC positions. This allows access to a PMC's front panel I/O and part of its circuit-side when mounted on a TPMB2 in a PC
backplane.
PMC/VME User I/O
The generic IEEE P1386 CMC specification defines a recommended routing strategy for PMC module's user I/O on VME carrier boards. The TPMB2 follows these recommendations by connecting the user I/O from one PMC to a DIN41618 plug (as used on a VME P2 connector) mounted on the top edge of the board. This allows VME P2 based I/O modules to be used with the TPMB2 and makes development of PMCs targeted at VME boards easier.
