|
Embedded Computing |
|
Data Recording & Storage |
|
Protocol & Bus Analyzers |
The MM-1500 combines the industry’s most powerful System-on-Chip, CoSine™, with the application optimized architecture of an Othello® VME carrier.
Mezzanine Sites
Mezzanine sites on the MM-1500 can support either PMCs or XMCs. Configured for PMC support, each PCI bus can operate in 32-bit or 64-bit PCI 2.3 mode at up to 66MHz or in 64-bit PCI-X mode at up to 133MHz. Configured for XMCs, the sites can support the Aurora™ protocol with four MGTs or Serial RapidIO x4.
Backplane Connectivity
In addition to having a VME320 2eSST interface on P1, the MM-1500 is the first VME board to include complete on-board Serial RapidIO switch fabric connectivity, with two independent Serial RapidIO ports on P0 per the VITA VXS 41.2 specification. Alternatively, two Aurora ports can be configured to P0 per the VITA 41.5 and VITA 55 draft standards.
SX55 and Virtex-4 DSP Slices
The MM-1500 is the first VME board to include the Virtex-4 SX™ series of FPGAs from Xilinx®. The SX series is unique in its significant hardware resources for DSP functions (see Xilinx Virtex-4 Family Overview).
The Virtex-4 SX55 is the largest device available in the SX family and offers the most DSP slices of any Xilinx FPGA. DSP slices are unique to the Virtex-4 FX, SX, and LX platforms. In the Virtex-II Pro and other FPGA families, only multipliers are offered thereby requiring all additions, subtractions, etc. to be implemented in logic.
CoSine Compute Nodes
The MM-1500 contains two independent CoSine Compute Nodes (CCNs). A single CCN is comprised of a CoSine Primary Device (Virtex-II Pro™ 2VP100), a CoSine Companion Device (Virtex-4 SX55) – see CoSine and CoSine Companion Device Configurations – and the following:
Aggregate memory bandwidth exceeds 20GB/s per CCN, providing a total of over 40 GB/s on the MM-1500.
PowerPC Processors and Infrastructure
Each of the two embedded PowerPCs in each 2VP100 is a fully functional computer, each with its own DDR array, programmable Flash, UART, and shared Ethernet. Processors can host device drivers, perform message passing, service interrupts, or execute floating point operations. Each processor includes a complete BSP with all internal SoC device drivers fully integrated so customers can download application files “out of the box”.
Reconfigurable Processing
Each of the SX55s have additional FPGA platform Flash to store multiple bitstreams. Because the principal System-on-Chip functionality is largely contained in the 2VP100 CoSine Primary Device, the MM-1500 is optimally designed for reconfigurable processing. This approach enables the SX55 CoSine Companion Devices, which contain User Programmable Logic, to be reconfigured by the 2VP100 CoSine Primary Devices without the 2VP100s needing to reconfigure themselves.
Temperature Sensing
The MM-1500 contains a CPLD that monitors the temperatures of the CoSine Primary Devices, CoSine Companion Devices, and primary circuit board to ensure proper operation. Status updates can be received by the CoSine PowerPC processors that can then make intelligent decisions, display status to user programmable LEDs, or communicate information over its Ethernet link to remote destinations.
Debug Ports
Debug ports include four RS-232 UART consoles, one board/system push button reset switch, and two processor JTAG debug ports. Debug ports are available out the front panel or backplane via P0.
Ruggedized Options
The MM-1500DR is a rugged, extended temperature air cooled board with an operating temperature of -40°C to +71°C. The MM-1500DTE is a rugged conduction cooled board with an operating temperature of -40°C to +85°C with cabling out the front panel. The MM-1500DR and MM-1500DTE were designed for optimal heat dissipation and deployment in environments that undergo severe shock and vibration.
* Note: while the MM-1500 is designed to meet these environmental requirements, formal qualification testing has not been performed to these levels. Please contact your local sales representative to discuss your program specific requirements.
Last updated: Mar 13 2008, 06:25PM