Memory Corner

For FPGA processing and CoSine™-based offerings, both memory bandwidth and latency are critical aspects to total product performance. The following includes brief summary descriptions of several memory technologies, citing their different characteristics and the rationale behind why we do or do not utilize a given technology in various product offerings.

SDRAM
While SDRAM clock frequencies are slower than DDR devices, they are still faster than many of the bus interfaces or I/O interconnects found on the boards utilizing SDRAM. This is important because higher memory bandwidths are not likely to provide meaningful improvements in latency or bandwidth for these products.

SDRAM has the advantage of being offered in a TSOP package, so devices can be reliably stacked four-high in the most rugged environments.

Another advantage of SDRAM is that it is offered in low power versions. This is important to the Umem line of NVRAM products. For Umem cards, when system power is lost the SDRAM devices are placed into a “sleep mode” wherein they are powered by on-board batteries. Utilizing low power SDRAM devices, this data retention time is extended beyond that experienced with standard power SDRAM devices.

DDR I
DDR I provides fast memory bandwidth and densities of up to 1Gb per device. Running at 133MHz, bandwidth for a 72-bit wide  array is approximately 2.16 GB/s. DDR I is the largest and fastest DRAM device available in a TSOP package. This is important because TSOP packages can be reliably stacked to further increase memory density. Running 133MHz is also an important consideration for the total size of a memory array, as faster clock rates (such as those required by DDR II) can result in loading issues for larger memory arrays. Even through the extensive use of drivers, creating very large memory arrays at higher frequencies can often pose reliability issues with regards timing skew.

DDR II
Faster than DDR I and requiring less power per megabyte, DDR II can provide strong advantages for bandwidth intensive applications. Differentiating attributes include on-device termination to provide better signal integrity to DQ and DQS lines. Devices are also scheduled to reach 2Gb by mid 2006.

DDR II’s primary disadvantage is its BGA package. As previously mentioned, stacking DDR I (TSOP package) is highly reliable, even going four-devices high and in the most rugged environments. But utilizing two-high DDR II (BGA) stacks is very new technology that has not yet been proven reliable in more rugged environments. Four-high DDR II BGA stacks are similar in this regard, being proven to work in very controlled, benign lab experiments but not fielded in volume applications, let alone applications with any type of rugged vibration requirements.

DDR II has an operating frequency of =/> 267MHz. While this results in bandwidth of over 4 GB/s for a typical 72-bit wide array, it poses challenges for larger arrays with regards maintaining acceptable timing margins in terms of loading.

This problem is compounded when using FPGAs for the memory controller. While large ASICs have the signal drive capabilities to drive deep memory arrays, this is a more difficult challenge for FPGAs.

With today’s leading FPGAs realistically supporting logic running clock frequencies of approximately 300MHz to 350MHz, ASICs are still able to run several times those frequencies and thus able to support faster memory devices.

Faster memory such as DDR II also has the drawback of consuming valuable high speed IO pins, as more address and data lines are required for each memory bank. Running at these rates also demands tight control over strobe delays, risking timing and raising reliability concerns.

DDR III
Although the specification for DDR III has not yet been released, first indications are that DDR III will start at 800 Mbits/sec and go as high as 1.5 Gbits/sec. It is also expected to run at a lower voltage than DDR II.

QDR II
QDR II is an improved version of QDR, which runs at higher frequencies, and lower voltages. It also has echo clocks and a wider read data valid window for easier capture of read data. Like QDR, it is optimized for very fast random access, for simultaneous read and write operations. QDR’s disadvantages compared to DDR are less density and higher power consumption per bit.

RLDRAM II
Reduced Latency DRAM is a double data rate (DDR) device, with the capability of up to 800 Mega-transfers/sec, and a data latency improved from DDR SDRAM. It shares reduced operating voltages and on chip termination with DDR II.

As most of our products are built upon FPGAs, it is notable that high speed memory interfaces present one of the most technically challenging areas of product development. This is particularly the case with the DDR and QDR devices that utilize source synchronous clocking to equalize signal rates. While providing an excellent method for supporting high speed memory interfaces, source synchronous clocking presents difficulties with aligning clock and data, and meeting setup and hold times, particularly on reads.

Until now, successful implementations of RLDRAM II with FPGAs have been limited. It is our opinion that FPGA high speed I/O pins and I/O blocks (IOBs) have not practically matched up well with the requirements of RLDRAM II that have consequently resulted in reliability issues.

NOR Flash
NOR Flash is byte accessible FLASH memory. It is most often used for non-volatile variable storage.

NAND Flash
NAND Flash is block accessible FLASH memory, usually based on 512 byte pages. It has a higher density than NOR Flash, but is only appropriate for storing block data. Due to the fact that most NAND Flash has bad bits, ECC (error checking and correction) is a necessity.

Download Flash Memory Types: NAND vs. NOR | Download Memory Mapping in a PCI System | Download Addressing Large Arrays over RACEway