FPGA Mezzanine Card (FMC/VITA 57) FPGA IO Mezzanine Standard

The FMC (VITA 57) standard provides an electro-mechanical standard for I/O mezzanine modules that work closely with FPGA processors. Thus, the mezzanine module would optimize the handling and formating of data. This standard aims to:

• Minimize latency
• Minimize system costs
• Maximize data through-put
• Reduce the complexity of FPGA designs
• Reduce system overhead

The standard defines two widths – single and double width. The single-width module measures 69 x 76.5 mm and is approximately half the size of a PMC module and supports a single connector, P1, to the carrier. The double-width module measures 139 x 76.5 mm and can support one or two connectors to the carrier, P1 and P2. The double-width FMC is for applications that require additional bandwidth to the carrier, more front panel space, or a larger PCB area. As is the case with most commercial PMC/XMC modules, most commercial FMCs will be single width.

There is a choice of two different connectors to interface the FMC to an FPGA on a carrier: a Low Pin Count (LPC) connector with 160 pins and a High Pin Count (HPC) connector with 400 pins. An FMC with the LPC connector can mate with a carrier that utilizes either an LPC or HPC connector. To support the widest range of FMCs, commercial carriers should utilize the HPC connector. The FMC specification was developed to enable FMCs to be supported on a wide range of existing form factors including but not limited to VME, CompactPCI, VXS, VPX, VPX-REDI, CompactPCI Express, AdvancedTCA, and AMC. Up to three FMCs can be fitted to a 6U VPX carrier.

The VITA 57 connector was chosen to ensure developers have the functionality and performance they need to allow them to move their I/O to a mezzanine card. The connector is designed to support single-ended and differential signaling up to 2 Gbps and signaling to an FPGA’s Multi-Gigabit Transceivers (MGTs) up to10 Gbps. The LPC connector provides 68 single-ended user-defined signals or 34 user-defined differential pairs, one MGT pair, clocks, a JTAG interface, and an I²C interface to optionally support the base IPMI commands. The HPC provides 160 single-ended user-defined signals or 80 user-defined differential pairs, 10 MGT pairs, and additional clocks.

To meet the demands of high-performance embedded computing, the FMC connector can support very high bandwidths; a single differential pair can provide 2 Gbps of bandwidth when clocked at 1 GHz since data can be transferred between the FMC and the carrier on the rising and falling edges of the clock. Even when clocked at a conservative 250 MHz, 32 differential pairs provide 2 GBps of bandwidth (250 MHz x 2 clock edges x 32 bits/8 bits/bytes). As an example, a quad 215 MSps 12-bit ADC FMC would transfer data at a rate of 1.29 GBps (215 x 12 bits/ADC x 4 ADCs/8 bits/byte). Utilizing 48 differential pairs (12 bits/ADC x 4) of the HPC connector clocked at 107.5 MHz (one half of the ADC sampling rate) would provide the required bandwidth to move the data from the four ADCs into the FPGA on the carrier.

The MGT interfaces are most useful for supporting protocols that run over multi-gigabit serial links. Moving the copper connectors or fiber optic transceivers from the base-FPGA design to an FMC mezzanine card makes it much easier for a single FPGA design to support various physical interfaces. Next-generation ADC and DAC chips that support the JEDEC JESD204 Standard (Serial Interface For Data Converters) interface will directly connect to one or more MGT ports of an FPGA. Converter chips supporting JESD204 interfaces, such as the Linear Technology LTC^®2274 16-bit 105Ms/s ADC, are expected to hit the market in 2008.

The FMC standard defines both air- and conduction-cooled form factors. The conduction-cooled form factor can receive all I/O over the P1 connector, or it can support front-panel I/O if necessary. Also defined in the standard is a front-panel bezel, which is very similar to PMC front-panel bezels.

The FMC standard provides for a great deal of flexibility in the interface between the FMC and carrier to support a wide range of functionality FMCs may provide. Flexibility in standards typically equates to incompatibility and fragmentation of the market, but this is not the case with the FMC standard. Even though there can be a wide variability in the number of I/O pins from FMC to FMC, due to the reconfigurability of FPGAs, as long as an FPGA has sufficient I/O pins mapped to the FMC site connector to support a particular FMC, the FPGA can be configured to support that FMC.